The present invention relates generally to the electronic transmission of digital data and more particularly to the transmission of digital data between two or more devices or integrated circuits.
In electronic devices using digital logic, digital data must be communicated from one circuit to another. This communication may take many forms including computer to computer, PC board to PC board, chip to chip, and between circuits on the same chip. As digital electronics have gotten faster, the speed at which these circuits communicate has increased. To communicate at these increased bandwidths, the time that data can be held valid on a given signal is decreased. As the data valid time is decreased, timing differences between these separate signals become large relative to the time data is valid on those signals. If one of these signals is a clock or other signal whose relationship to another signal is critical for proper communication, erroneous or incorrect data may be latched into the receiving circuit.
Accordingly, there is a need in the art for an improved method of communicating digital data that increases the length of time available for a circuit to read data without reducing the amount of data communicated. To ensure broad application, it is desirable that this method be adaptable to different data rates and timing differences. Finally, it is desirable that this method be adaptable to different circuit technologies and environments.
In a preferred embodiment, the invention transfers data using three logic states on a differential pair of wires. The three states are: a first line a threshold higher than a second line, the second line a threshold higher than the first line, and when both lines are approximately equal. The presence of three states allows the receiving circuit to recognize the beginning and end of a valid data bit.
In a preferred embodiment, two states are used to generate two strobes. One strobe will be active when the first line is greater than the second and the other strobe will be when the second line is greater than the first. When both lines are approximately equal, neither strobe is active. The strobes are used to increment a counter, and latch in a logical high or a logical low depending on which strobe is active. The counter is used to determine which register is to latch in the logical high or the logical low. This allows the register to hold the logical high or logical low for N times as long, where N is the number of registers used to hold data received via this pair of differential wires.